Electrical property tests and potential defect burn-in screening tests of semiconductor devices on a wafer have been conducted with a probe card including many probes. A number of semiconductor devices are formed on the semiconductor wafer and alignment patterns used in conducting a test of the wafer are provided on the wafer.
FIG. 25 shows an enlarged view of a portion of conventional semiconductor wafer. Shown in FIG. 25 is an alignment pattern provided for one semiconductor device.
In FIG. 25, an ion probe test on the internal circuitry of the semiconductor device 2 formed on the semiconductor wafer 1 is conducted with a probe card including a number of probes 3.
In this probe test, semiconductor devices 2 formed on the semiconductor wafer 1 are tested individually, or a number of semiconductor devices 2, for example, 2 to 16 semiconductor devices 2, are tested at a time.
A number of electrode terminals 4 are formed in each semiconductor device 2 and a pair of adjacent electrode terminals among the electrode terminals 4 is used as an alignment pattern 5. The alignment pattern 5is used for aligning probes 3 of the probe cards with electrode terminals 4 of the semiconductor device 2.
When multiple probes 3 are brought into contact with the electrode terminals 4 in the probe test, the alignment pattern 5 is used to electrically check to determine whether the probes 3 are properly aligned with the electrode terminals 4. If they are misaligned, the alignment pattern 5 is used to re-align the probes 3 and the electrode terminals 4.
Functions of the alignment pattern 5 will be described below in detail. In the following description, a pair of electrode terminals forming the alignment pattern 5 will be identified as an electrode terminal 9 and a conductor electrode terminal 12, thereby to distinguish from other electrode terminals 4 that are not included in the alignment pattern 5.
The alignment pattern 5 comprises a first electrode terminal section 6 and a second electrode terminal section 7. The first electrode terminal section 6 includes a detector electrode terminal 8 in the form of a ring, an electrode terminal 9 connecting to the internal circuitry of the semiconductor device 2, and an interconnection 10 connecting the detector electrode terminal 8 with the electrode terminal 9.
The second electrode terminal section 7 comprises a conductor electrode terminal 12 that is connected to neither the internal circuit of the semiconductor device 2 or an external terminal. The conductor electrode terminal 12 is provided inside and separated from the detector electrode terminal 8 of the first electrode terminal section 6 by a gap 11.
The semiconductor device 2 is covered with a protective film, portions of which are removed to provide openings 13 at positions corresponding to the electrode terminals 4. The detector electrode terminal 8 of the first electrode terminal section 6 and the conductor electrode terminal 12 of the second electrode terminal section 7 are exposed in one opening 13 and the electrode terminal 9 of the first electrode terminal section 6 is exposed in another opening 13.
A method for using the alignment pattern 5 in a probe test to check to determine whether each probe 3 of a probe card is properly aligned with each electrode terminal 4 of the semiconductor device 2 will be described below.
The probes 3 of the probe card is brought into contact with the electrode terminals 4 of the semiconductor device 2. In doing so, one of two probes 3 to which different voltages are applied is brought into contact with the electrode terminal 9 in the first electrode terminal section 6 and the other with the conductor electrode terminal 12 in the second electrode terminal section 7. Then, current flowing between the probes 3 is monitored.
If both probes 3 are properly positioned with respect to the electrode terminal 9 and the conductor electrode terminal 12 and one of the probes 3 is in contact with only the conductor electrode terminal 12 without departing from the conductor electrode terminal 12, only internal output signals from the electrode terminal 9 are observed between the probes 3.
From this result of observation, it is determined that each probe 3 of the probe card is properly in contact with each electrode terminal 4 of the semiconductor device 2.
If both of the probes 3 are out of proper alignment with the electrode terminal 9 and the conductor electrode terminal 12 and one of the probe 3 is off the conductor electrode terminal 12 and is in contact with the detector electrode terminal 8 in the first electrode terminal section 6, both probes 3 are in contact with the first electrode terminal section 6 and signals other than internal output signals from the electrode terminal 9 are observed between the probes 3 in addition to internal output signals.
It is determined from this result of observation that the probes 3 of the probe card are in contact with the electrode terminals 4 of the semiconductor device 2 in an improper manner.
FIG. 26 is a schematic diagram showing another conventional alignment pattern.
The alignment pattern 5 in FIG. 26 is provided in the scribe line 15 between semiconductor devices 2 formed on a semiconductor wafer 1. The alignment pattern 5 comprises three electrode terminals 4 arranged in line and an interconnection 16 interconnecting them. The electrode terminal 4 at the center is smaller than the other electrodes at the sides. Openings 13 provided in the protective film of the semiconductors 2 have shapes in accordance with the sizes of the side electrodes 4 and the center electrode terminal 4.
A method for using the alignment pattern 5 in a probe test will be described below. The probes 3 of a prove card are brought into contact with the electrode terminals 4 of a semiconductor device 2. In doing so, one of three probes 3 is brought into contact with the electrode terminal 4 at the center and the other two probes with the electrode terminals 4 at the sides. Then, electric signals at the center electrode terminal 4 are monitored while a voltage is being applied to the electrode terminals 4 at the sides.
If the center probe 3 is not off the center electrode terminal 4 and the tree probes 3 are in contact with the side electrode terminals 4 and the center electrode terminal appropriately, electric signal from the center probe 3 can be observed.
From this result of observation, it is determined that each probe 3 of the probe card is properly in contact with each electrode terminal 4 of the semiconductor device 2.
On the other hand, if the center probe 3 is off the center electrode terminal 4, no electric signal from the center probe 3 can be observed.
It is determined from this result of observation that the probes 3 of the probe cared are out of alignment with the electrode terminals 4 of the semiconductor device 2.
Documents about the conventional art include:    1. Japanese Patent Laid-Open No. 5-343487    2. Japanese Patent Laid-Open No. 6-045419
Technologies for creating as many semiconductor devices as possible on one semiconductor wafer are becoming increasingly important because of requirements in technology trends and cost advantage. Accordingly, the size of semiconductor devices is being reduced by miniaturizing the internal circuits of semiconductor devices and reducing the distance between electrode terminals or providing circuit elements directly underneath the electrode terminals or under a location close to the electrode terminals.
This increases the possibility that when probe tips are brought into contact with the electrode terminals of the semiconductor devices on a wafer during an electrical property test or a burn-in test, the probe tips contact the semiconductor devices in locations off the electrode terminals.
An electrode terminal is exposed in an opening in a nonconductor layer that covers the semiconductor device. If the tip of a probe is out of proper alignment with the electrode terminal, the probe can damage the nonconductor layer around the opening or the load concentrating on the tip of the probe can damage a circuit element under the electrode terminal.
Using a probe card to conduct an electrical property test or a burn-in test of semiconductor deices on a wafer has the following problems.
One problem is that plastic deformation of probes of a probe card can occur when they contact electrode terminals. Another problem is that because the area of an electrode terminal is well larger than the area of contact between the electrode terminal and the probe tip, the probe tip can slide on the electrode terminal under pressure applied on the probe during the contact and thus the probe tip cannot accurately be aligned with the center of the electrode terminal.
As a result, the point of contact of the probe tip on the electrode terminal is gradually displaced from the center of the electrode terminal as the test progresses. Eventually, the probe tip moves off the electrode terminal exposed in the opening in a protective film, that is, the probe tip contacts the protective film around the opening. This can damage the protective film or, in worse cases, affect electrical properties of the device.
Nowadays, such defects in appearance or reliability can be detected and removed only by visual inspections under a microscope which require a large number of man-hours or a costly visual inspection machine.
Another problem is that defects undetectable by visual inspections, such as defects that are caused by minute imperfections in a nonconductor layer under an electrode terminal and affect electrical properties can remain at an electrical property testing stage and man-hours for removing the defects is required.
In current tests using a probe card with many probes, when a probe contacts an electrode terminal, a considerably large load concentrates on the thin tip of the probe. For example, a load of 5 g applied to the probe tip having a diameter of 20 μm is equivalent to a pressure of 1600 kg/cm2.
Therefore, if a circuit element is formed in a nonconductor layer directly underneath an electrode terminal or under a location close to an electrode terminal of a semiconductor device, damage or minute imperfections can be caused in the circuit element as well as the nonconductor layer, resulting in degradation of electrical properties of the semiconductor device. Consequently, the yields are reduced and reduction in the manufacturing costs becomes difficult.
Moreover, if atmosphere temperature is kept high while a probe is in contact with an electrode terminal in a burn-in test on a wafer, the probe, typically made of a tungsten-based material, and the electrode terminal can be oxidized at the point of contact. Consequently, the electric resistance would increase and stable testing would be prohibited.
To prevent such oxidization of contact points, burn-in tests have been performed in an inert atmosphere. This poses the problem of increasing manufacturing costs since a large amount of inert gas is used.
An object of the present invention is to improve the efficiency of tests on high-density semiconductor devices having circuit elements directly underneath electrode terminals or under a location close to electrode terminals, that is, electrical property tests and potential defect burn-in screenings of devices on a wafer. In particular, an object of the present invention is to provide a semiconductor wafer that has alignment patterns to allow bump electrodes and corresponding electrode terminals of semiconductor devices to contact with each other without misalignment in a test using a contactor having multiple bump electrodes, and a testing method therefor.